טל כהן — ספרינט ראיונות
Post-Silicon / ATE Test

"Validation asks: does the design work? Production test asks: is this specific unit built correctly?"

Set bit 5: reg |= (1 << 5);   Clear: reg &= ~(1 << 5);   Toggle: reg ^= (1 << 5);

"My test programs in C did exactly this pattern — configure, stimulate, measure, log — just from the tester side instead of on-chip. The register-level debug skill is identical."

"Loopback modes (near-end / far-end) with PRBS patterns, measure BER, eye margining via the on-chip eye monitor, sweep voltage and temperature corners. On ATE specifically — loopback plus on-chip instruments, because tester bandwidth is limited."

"The LTSSM walks through receiver detect, polling with training sequences, configuration negotiating width and speed, then L0 — active. Production test verifies the link trains to full width and speed across corners."

"Network ICs are SerDes-dominated — huge numbers of high-speed lanes — so production test is largely about high-speed I/O coverage and loopback strategies."

"At Tower I've spent seven years as a test engineer inside the fab — developing test programs in C, debugging at wafer level, and working directly with process and device teams. It's a different vantage point from product ATE test: I've seen why silicon fails, not just that it fails. The platform specifics of commercial ATE are a ramp I'll close quickly — what I bring on day one is test program development, structured debug, silicon intuition, and the discipline of production: every decision I make affects yield and cost on a live line."

"I'm a test engineer with seven years at Tower Semiconductor's Fab2 in Israel. I develop and debug test programs in C for wafer-level testing, optimize test flows, and work hands-on with engineering teams on silicon debug. I completed my EE degree at the Technion while working full-time, specializing in micro- and nano-electronics. What I'm looking for now is to move from the foundry side to product-level test — taking the silicon understanding I built inside the fab and applying it to ATE test development for complex ICs. That's why this role caught my attention."

"Seven years gave me deep wafer-level and process-side test experience, but I've reached the ceiling of that scope. I want to own product test — the full test program lifecycle, from bring-up to production release, on complex digital products. That doesn't exist at a foundry; it exists at companies like NVIDIA."

"Two reasons. The networking products — the Mellanox heritage — are SerDes-dense, test-intensive ICs where test engineering genuinely matters to the business. And NVIDIA is shipping at a volume and pace where production test decisions have real impact. I want my work measured in yield and test cost on products that ship in the millions."

"Start from the escapes: RMA and field-failure data tells you exactly what current tests miss. Then three levers — targeted new tests for those failure modes, working with the DFT team for higher structural coverage on weak blocks, and adding parametric and margin tests at corners for marginal behavior. Coverage additions get justified by escape data, not by intuition."

"Data first: per-test fail rates and time from production datalogs. Tests that never uniquely fail are removal candidates — with an escape-risk review. Then structural moves: reorder so likely failures hit early, increase multi-site parallelism, run independent blocks concurrently. At Tower I optimized test code for execution time, so I think in milliseconds by habit."

"Reproduce, isolate one variable at a time, shmoo voltage and temperature, compare datalogs good versus bad, root cause — and always close the loop: add a production screen so it can't escape again."

"With designers I bring data, not opinions — datalogs and shmoo plots that show exactly where silicon deviates. With DFT, I come with coverage gaps backed by escape data. With manufacturing, I've sat on their side at Tower for seven years — I know they need clear limits, clear disposition rules, and fast response when the line is down."

"My experience is wafer-level and foundry-side, so commercial ATE platforms and packaged-part test flows are a ramp for me. I'm direct about that. The mitigation is that I've already done the core job — test program development and silicon debug — and I learn platforms fast: I finished a Technion degree while working full-time, so structured fast learning is something I've proven, not something I claim."

"Three things. C-based test development and debug for seven years — the daily work of this role. Silicon understanding from inside the fab — I know why devices fail, which makes my debug faster and my coverage decisions smarter. And production discipline — I've worked where every test decision hits yield and cost the same day. The gaps I have are platform-specific and they close in months; the foundation doesn't."

S: "A test program at Fab2 began failing intermittently on [product/process], flagging good wafers and threatening [holds / yield loss]."

T: "I owned root cause — the line couldn't tolerate false rejects."

A: "I reproduced the failure pattern across [N wafers], isolated variables one at a time — program version, probe card, conditions — and found the failures correlated with [specific condition]. I traced it in the C code to [root cause], fixed [the settling time / limit logic], and verified across [M] lots."

R: "False failures dropped to zero, recovered [X%] yield-reporting accuracy, and I added a monitor so the drift gets flagged before it bites again."

S: "We needed test coverage for [new device/parameter] entering production."

T: "Develop the test program in C: sequence, limits, and an execution-time budget."

A: "I wrote the measurement routines, set limits from characterization data with the device team, and optimized the code — [restructured loops / removed redundant settling / batched measurements] — cutting execution time by [X%]."

R: "Released to production; it has run on [Z wafers/lots] since, saving [time per wafer]."

S: "Process engineering saw [anomaly] and suspected the test, while my data pointed at the process."

T: "Resolve it without finger-pointing and without holding the line longer than necessary."

A: "I designed a split experiment — same wafers, [two programs / two systems / golden-unit correlation] — and presented the isolation data in one page both teams could read."

R: "Root cause confirmed as [X] in [days]; we updated [the spec / the test], and the experiment format became how we settle test-vs-process questions."

S: "I completed my Technion EE degree while working full-time at Tower — five years of parallel load."

T: "Maintain full performance at work while finishing a Technion engineering program."

A: "I ran a strict system — [mornings for study / structured weekly planning] — and deliberately routed coursework into work value: my [VHDL / TCAD / device physics] courses fed directly into how I debug at wafer level."

R: "Graduated June 2024, specializations in micro/nano-electronics and energy systems, zero performance issues at work. When I say I'll ramp on a new ATE platform quickly — this is the evidence."

S: "[A test program / area] had recurring issues and no clear owner."

T: "Nobody asked me to take it. I took it."

A: "I documented the failure history, fixed [N issues] in the C code, wrote the missing process documentation, and became the point of contact."

R: "Escalations on it dropped [X%], and the documentation became the team reference. I don't wait for ownership to be assigned."

S: "Test time on [flow] was a bottleneck — [N hours per wafer/lot] on a loaded line."

T: "Reduce time without losing coverage — and prove no coverage was lost."

A: "I profiled the program, found [redundant measurements / inefficient sequencing], restructured the code, and validated against [historical datalogs / split lots] that detection was unchanged."

R: "[X%] test-time reduction, [capacity/cost impact], with documented proof of equivalent coverage."

TAL COHEN
Test Engineer | Post-Silicon & ATE Test Development | Haifa, Israel
[phone] · [email] · [LinkedIn]

Professional Summary
Test Engineer with 7 years at Tower Semiconductor developing and debugging C-based test programs for wafer-level production test. Deep silicon and process understanding from inside the fab; track record of test-time optimization and production debug. Technion EE graduate (completed while working full-time). Targeting post-silicon / ATE test development roles for complex ICs.

Experience — Test Engineer, Tower Semiconductor, Fab2 (2019–Present)

• Developed and maintained [Y] production test programs in C for wafer-level test across [Z] products/process flows, supporting a high-volume manufacturing line.
• Reduced test execution time by [X%] through code optimization and measurement-sequence restructuring, saving [N] minutes per wafer.
• Debugged [N+] complex test and silicon failures hands-on using structured isolation (shmoo, split experiments, datalog correlation), cutting average resolution time by [X%].
• Eliminated recurring false-failure events on [flow], recovering [X%] reported-yield accuracy and preventing unnecessary wafer holds.
• Partnered with process, device, and product engineering teams to root-cause test-vs-process discrepancies using designed split experiments.
• Authored test process documentation adopted as the team standard, reducing escalations by [X%].

Education
BSc Electrical Engineering, Technion — Israel Institute of Technology, June 2024.
Specializations: Micro & Nano Electronics; Energy and Supply Systems. Completed while working full-time.

Technical Skills
Programming: C, C++, Python, Bash, MATLAB
Hardware description: VHDL, Verilog
Test & analysis: Test program development, wafer-level test, debug methodology, JMP
EDA / device tools: Cadence Virtuoso, Synopsys TCAD, KLayout
Domain: Semiconductor process & device physics, yield analysis, production test flows, DFT concepts (scan, BIST, JTAG)

Test Engineer with 7 years at Tower Semiconductor developing C-based test programs for wafer-level production test. I've spent my career inside the fab — which means I debug silicon knowing why it fails, not just that it fails. Technion EE graduate (earned while working full-time). Now moving toward post-silicon / ATE test development for complex ICs, where production test decisions directly drive yield, cost, and quality. Strengths: C test development, structured debug, test-time optimization, cross-team root cause work. Open to Post-Silicon / ATE / Product Test roles.

Hi [Name], I'm a test engineer with 7 years at Tower Semiconductor (C test program development, wafer-level production test, silicon debug) and a Technion EE degree. I'm targeting post-silicon / ATE test development roles. Is [role/team] still open? Happy to send my resume. Thanks, Tal

Hi [Name], I saw you're on [team] at NVIDIA. I'm a test engineer at Tower Semiconductor — 7 years of C test program development and silicon debug at wafer level, Technion EE. I'm very interested in the [exact role title] position and would appreciate 2 minutes of your perspective on the team — and if it seems like a fit, I'd be grateful for a referral. Happy to send my resume. Thanks! Tal